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项目作者: sujoyyyy

项目描述 :
Lab work for VLSI for computer science. It formalizes the notion of hierarchical design of Integrated Circuits and abstracts the notion of design of integrated circuits.
高级语言: Verilog
项目地址: git://github.com/sujoyyyy/VLSI.git
创建时间: 2020-08-07T12:57:58Z
项目社区:https://github.com/sujoyyyy/VLSI

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