项目作者: Logician724
项目描述 :
A Quartus prime project that implements a 0 to 99 counter on 7 segment display using Altera DE10-Lite board
高级语言: Verilog
项目地址: git://github.com/Logician724/digital_timer.git
digital_timer
A Quartus prime project that implements a 0 to 99 counter on 7 segment display using Altera DE10-Lite board