项目作者: Logician724

项目描述 :
A Quartus prime project that implements a 0 to 99 counter on 7 segment display using Altera DE10-Lite board
高级语言: Verilog
项目地址: git://github.com/Logician724/digital_timer.git
创建时间: 2017-11-03T17:39:49Z
项目社区:https://github.com/Logician724/digital_timer

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digital_timer

A Quartus prime project that implements a 0 to 99 counter on 7 segment display using Altera DE10-Lite board