项目作者: mihir8181

项目描述 :
This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other details
高级语言:
项目地址: git://github.com/mihir8181/VLSI-Design-Digital-System.git
创建时间: 2018-11-09T08:30:20Z
项目社区:https://github.com/mihir8181/VLSI-Design-Digital-System

开源协议:

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VLSI-Design-Digital-System

This is a VLSI designing Project. This Project is created using Cadence Virtuoso software.

It Includes Basic Logic Gates to simple ALU design.

Logic Gates like AND,OR,NAND,NOR XOR. Also used this Logic Gates to design Inverter, Transmission Gate, 1-Bit Add/Subtract, 4-Bit Adder, Multipler, Divider, D-FlipFlop, 2:1, 8:1 Multiplexer.

Check PDF for more details. There is screenshots of all circuit’s Schematic, Symbol, testbench, Simulation, Layout, Postlayout-simulation, DRC, LVS and calulations.


D-FlipFlop
Schematic

D-FlipFlop TestBench

D-FlipFlop Layout

8:1 MUX
Schematic

8:1 MUX TestBench

8:1 MUX Layout

4-Bit Adder
Schematic

4-Bit Adder TestBench

4-Bit Adder Layout

4-Bit Multipler
Schematic

4-Bit Multipler TestBench

4-Bit Multipler Layout

4-Bit Multipler Waveform

4-Bit Divider
Schematic

4-Bit Divider TestBench

4-Bit Divider Layout

4Bit_Adder_LVS_1650003649474.pdf
4Bit_Adder_SCH_1650003649533.pdf
4Bit_Adder_Symbol_1650003649553.pdf
4Bit_Adder_Testbench_1650003649600.pdf
4Bit_adder_Layout_1650003649681.pdf
4Bit_Divider_LVS_1650003649712.pdf
4Bit_Divider_Layout_1650003649825.pdf
4Bit_Divider_SCH_1650003649892.pdf
4Bit_Divider_Symbol_1650003649950.pdf
4Bit_Divider_TestBench_1650003649992.pdf
4Bit Multiplier Graph_1650003650037.pdf
4Bit_Multipiler_Symbol_1650003650111.pdf
4Bit_Multipiler_Testbench_1650003650146.pdf
4Bit_Multiplier_LVS_1650003650209.pdf
4Bit_Multiplier_Layout_1650003650297.pdf
4Bit_Multiplier_Sch_1650003650346.pdf
8to1MUX_LVS_1650003650391.pdf
8to1MUX_Layout_1650003650519.pdf
8to1_MUX_SCH_1650003650537.pdf
8to1_MUX_Symbol_1650003650578.pdf
8to1_MUX_Testbench_1650003650641.pdf
D_FlipFlop_LVS_1650003650671.pdf
D_FlipFlop_Layout_1650003650798.pdf
D_FlipFlop_SCH_1650003650861.pdf
D_FlipFlop_Symbol_1650003650914.pdf
D_FlipFlop_TestBench_1650003650939.pdf
VLSI_2A_1650003651497.pdf
VLSI_2B_1650003652196.pdf
VLSI_2A_1650102079005.pdf
VLSI_2B_1650102080687.pdf
D_FlipFlop_TestBench_1650102078018.pdf
D_FlipFlop_LVS_1650102077026.pdf
D_FlipFlop_Layout_1650102077511.pdf
D_FlipFlop_SCH_1650102077727.pdf
D_FlipFlop_Symbol_1650102077779.pdf
8to1MUX_Layout_1650102075906.pdf
8to1_MUX_SCH_1650102076151.pdf
8to1_MUX_Symbol_1650102076214.pdf
8to1_MUX_Testbench_1650102076415.pdf
8to1MUX_LVS_1650102075587.pdf
4Bit_Multiplier_Layout_1650102074483.pdf
4Bit_Multiplier_Sch_1650102074890.pdf
4Bit_Divider_TestBench_1650102073121.pdf
4Bit Multiplier Graph_1650102073425.pdf
4Bit_Multipiler_Symbol_1650102073475.pdf
4Bit_Multipiler_Testbench_1650102073655.pdf
4Bit_Multiplier_LVS_1650102073862.pdf
4Bit_Divider_Layout_1650102072219.pdf
4Bit_Divider_SCH_1650102072756.pdf
4Bit_Divider_Symbol_1650102072871.pdf
4Bit_Adder_Testbench_1650102071035.pdf
4Bit_adder_Layout_1650102071537.pdf
4Bit_Divider_LVS_1650102071851.pdf
4Bit_Adder_LVS_1650102070424.pdf
4Bit_Adder_SCH_1650102070709.pdf
4Bit_Adder_Symbol_1650102070798.pdf