项目作者: egk696

项目描述 :
A Fault Tolerant Globally-Asynchronous-Locally-Synchronous Inter-Chip Communication Bridge on FPGAs
高级语言: VHDL
项目地址: git://github.com/egk696/InterChip_Bridge.git
创建时间: 2017-10-20T11:21:21Z
项目社区:https://github.com/egk696/InterChip_Bridge

开源协议:MIT License

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InterChip Bridge

This repository hosts the developed code that implements the proposed InterChip Communication Bridge presented in:

E.Kyriakakis, K. Ngo and J.Öberg, “Implementation of a Fault-Tolerant, Globally-Asynchronous-Locally-Synchronous, Inter-Chip NoC Communication Bridge on FPGAs”, In proceeedings of NORCAS-2017, Linköping, Sweden.

Structure

  • bridge_src: is the main VHDL codebase for the developed interchip bridge component
  • other_src: is a VHDL codebase for any other developed components used in the demo projects