项目作者: amamory-verification
项目描述 :
Hardware Formal Verification
高级语言: Verilog
项目地址: git://github.com/amamory-verification/hw-formal-verif.git
This repository containts the assignements for the course
Functional Verification on Digital Systems II, from the
Graduate Program of Computer Science at PUCRS University.
These assignments are divided in three levels:
- Tutorial level: which is a step-by-step tutorial to help the students to know the tools and their setup. See the directory xtea-cripto-core for more.
- Entry Level: correspond to very basic designs, suggested as an initial steps for the students to build their own FV environments. See the vending-machine and formal-verif-book dircs for more.
- Master Level: correspond to the main assignment of the semester, which is more challenging. It is a Hemes router for networks-on-chip. See the noc-router dir for more.
For more information, refer to the Moodle webpage.