行业智能>> RISC-V_CPU>> 返回
项目作者： RipperJ

项目描述 ：
RISC-V 32i CPU and Assembler
高级语言： Python
项目地址: git://github.com/RipperJ/RISC-V_CPU.git
创建时间： 2021-03-13T01:42:13Z
项目社区：https://github.com/RipperJ/RISC-V_CPU
开源协议：
下载


RISC-V 32i CPU and Assembler

This is one of the course project materials for HKUST ELEC-5140 Advanced Computer Architecture, where students are encouraged to enhance the structural model and improve its performance. This project is alive, maintained by linfeng.du@connect.ust.hk"">linfeng.du@connect.ust.hk. Any discussion or suggestion would be greatly appreciated!

Project Tree

  1. RV32i directory contains a Vivado project of RISC-V CPU written in verilog, which implements a 5-stage single-issue processor, supporting 31 basic instructions from RV32I base instruction set.

  2. RISC-V_Assembler directory contains an assembler to translate RISC-V instruction assembly into hexadecimal format, which could be easily directly loaded to instruction memory through $readmemh during Vivado simulation.

  3. tests directory contains benchmark written in RV32i assembly. Vec_Mul is a basic coding example.

Assembly Manual

What this assembler supports:

  • R-type:
    1. add s1, t1, t2 # s1 = t1 + t2
  • I-type:
    1. slti s1, t1, 3 # if t1 < 3: s1 = 1; else: s1 = 0;
  • Load / Store:
    1. lw s1, 4(t1) # s1 = *(t1 + 1) // 4 means 4 bytes == 1 word (int size)
    2. sw s1, 4(t1)
  • Branch:
    ```

    Using immediate value for address is OK

    beq t1, t2, 0x1000

    A more convenient way is using labels, like:

This_Is_A_Label:

…

… do whatever you want

…

beq t1, t2, This_Is_A_Label // if t1 == t2, then jump to the first instruction after label “This_Is_A_Label”

  1. * LUI / AUIPC:

lui x2, 0x12345 # x2 = 0x12345000
addi x2, x2, 0x678 # x2 = 0x12345678
auipc x3, 0x0100 # x3 = 0x00100000 + PC

  1. * JAL / JALR:

jal x1, SOME_LABEL # or some immediate value as address
jalr x0, x1, 0 # only immediate value is allowed for the third parameter!

  1.            # by the way, this is equal to "jr ra" in its effect
  2.            # you can realize calling a function with "jal" and "jalr"
  1. * comments:

This is a line of comment

// This is also a line of comment
add s1, s2, s3 # This is a line of comment following one instruction
add s1, s2, s3 // This is also a line of comment following one instruction

  1. * Others

1. Case Insensitivity

add s1, t1, t2 // OK
ADD s2, t1, t1 // also OK

2. Supporting both Register Name and ABI Name

// Instead of using register name ‘x0’, ‘x1’, you can also use ‘zero’, ‘ra’,
// which makes your assembly more readable
```

TODO

  • Assembler

  • CPU

    • To support other basic instructions
      • LB, LH, LBU, LHU
      • SB, SH
      • FENCE, FENCE.I
      • ECALL, EBREAK
      • CSRR*