项目作者: 9231058

项目描述 :
Dr.SahebZamani FPGA Homework
高级语言: VHDL
项目地址: git://github.com/9231058/FPGA-Homework.git
创建时间: 2016-01-30T18:35:21Z
项目社区:https://github.com/9231058/FPGA-Homework

开源协议:GNU General Public License v3.0

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D-01-HDL-_1647867015282.pdf
D-02-HDL-_1647867015326.pdf
D-03-DataTypes-_1647867015404.pdf
D-04-Operators-_1647867015442.pdf
D-05-Seq-Conc-_1647867015514.pdf
D-06-Design Flow_1647867015773.pdf
D-07-Synthesizability and FSM1_1647867015875.pdf
D-07-Synthesizability and FSM2_1647867015918.pdf
D09_Embedded_1647867016040.pdf
D10-Design Techniques_1647867016162.pdf
D12-Area Optimization_1647867016297.pdf
D13_Speed Optimization1_1647867016434.pdf
D14_Speed Optimization2_1647867016573.pdf
HW-1-sol_1647867013523.pdf
HW-1_1647867013601.pdf
HW-2-sol_1647867013667.pdf
HW-2_1647867013687.pdf
HW-3-sol_1647867013717.pdf
HW-3_1647867013767.pdf
HW-4-sol_1647867013795.pdf
HW-4_1647867013807.pdf
HW-6-sol_1647867013828.pdf
HW-6_1647867013958.pdf
Project1_1647867013996.pdf
Project2_1647867014079.pdf
Project3_1647867014138.pdf
01_intro_1647867014243.pdf
02-industry-_1647867014349.pdf
03_PLDvsFPGA-_1647867014372.pdf
03_design_cycle_1647867014409.pdf
04-DesignCycle-_1647867014439.pdf
A05-Programming_1647867014494.pdf
A06-LB_1647867014510.pdf
A07-Connections_1647867014599.pdf
A08-Commercial Chips_1647867014692.pdf
A08-Cyclone-Stratix_1647867014750.pdf
A09-Spartan-Virtex_1647867014916.pdf
A10-CoolRunner-Axcelerator_1647867015142.pdf
D12-Area Optimization_1649351007005.pdf
D13_Speed Optimization1_1649351007104.pdf
D14_Speed Optimization2_1649351007172.pdf
D-02-HDL-_1649351006435.pdf
D-03-DataTypes-_1649351006492.pdf
D-04-Operators-_1649351006524.pdf
D-05-Seq-Conc-_1649351006647.pdf
D-06-Design Flow_1649351006722.pdf
D-07-Synthesizability and FSM1_1649351006763.pdf
D-07-Synthesizability and FSM2_1649351006888.pdf
D09_Embedded_1649351006936.pdf
D10-Design Techniques_1649351006977.pdf
A08-Cyclone-Stratix_1649351005153.pdf
A09-Spartan-Virtex_1649351005390.pdf
A10-CoolRunner-Axcelerator_1649351005727.pdf
D-01-HDL-_1649351005798.pdf
01_intro_1649351003966.pdf
02-industry-_1649351004035.pdf
03_PLDvsFPGA-_1649351004096.pdf
03_design_cycle_1649351004139.pdf
04-DesignCycle-_1649351004202.pdf
A05-Programming_1649351004290.pdf
A06-LB_1649351004520.pdf
A07-Connections_1649351004647.pdf
A08-Commercial Chips_1649351004941.pdf
Project1_1649351003079.pdf
Project2_1649351003663.pdf
Project3_1649351003762.pdf
HW-2-sol_1649351002500.pdf
HW-2_1649351002579.pdf
HW-3-sol_1649351002635.pdf
HW-3_1649351002675.pdf
HW-4-sol_1649351002770.pdf
HW-4_1649351002839.pdf
HW-6-sol_1649351002872.pdf
HW-6_1649351002964.pdf
HW-1-sol_1649351001527.pdf
HW-1_1649351001626.pdf