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项目作者： zbnt

项目描述 ：
Hardware cores for generating, capturing and modifying network traffic using Xilinx FPGAs/SoCs
高级语言： SystemVerilog
项目地址: git://github.com/zbnt/hardware.git
创建时间： 2019-08-24T23:25:15Z
项目社区：https://github.com/zbnt/hardware
开源协议：Mozilla Public License 2.0
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zbnt/hardware

HDL code and block designs for ZBNT, a system for generating, capturing and modifying network traffic.

Requirements

Hardware

This repository includes block designs for the following boards:

Software

Others

  • For building the bitstreams, a system with at least 16GB of RAM is highly recommended

Building

  1. Clone this repository, make sure all dependencies are installed before proceeding.
  2. Initialize and fetch the required submodules:
  1. git submodule init
  2. git submodule update
  1. Add Vivado tools to PATH by sourcing the settings64.sh script in the installation directory:
  1. source /opt/Xilinx/Vivado/2021.1/settings64.sh
  1. cd to the root directory of this repository and run make
  1. # Build bitstreams for all supported devices
  2. make
  4. # Build bitstreams only for the specified device
  5. make zedboard
  6. make ultra96
  7. make netfpga_1g_cml
  9. # Use the NUM_JOBS environment variable to control the number of parallel synthesis jobs
  10. # The default value is 1, incrementing this number reduces synthesis time but increments
  11. # the amount of RAM required.
  12. NUM_JOBS=4 make zedboard

License

  • The source code included in this repository is subject to the terms of the Mozilla Public License, v2.0. A copy is available in LICENSE.txt and Mozilla’s website. This excludes code referenced as a submodule, located in the external/ directory.
  • The block designs depend on IP cores available for free as part of the Xilinx Vivado Design Suite, and licensed under the terms of the Xilinx End User License. The source code for those cores is not distributed as part of this repository.