项目描述 ：
In this shift register, we can send the bits serially from the input of left most D flip-flop. Hence, this input is also called as serial input. For every positive edge triggering of clock signal, the data shifts from one stage to the next. In this case, we can access the outputs of each D flip-flop in parallel. So, we will get parallel outputs from this shift register.

高级语言： Verilog

项目主页：

项目地址: git://github.com/mnmhdanas/Serial-IN-Parallel-OUT.git

创建时间： 2021-07-24T15:50:04Z
项目社区：https://github.com/mnmhdanas/Serial-IN-Parallel-OUT
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