RTL and python for using the ADAU1761 audio codec on the Pynq-Z2 board from TUL
RTL and python for using the audio codec with Pynq.
Additional audio DSP project to demonstrate functionality:
src/rtl
adau1761.sv
toplevel of DSP chain with I2S interface to audio codecadau1761_wrapper.v
verilog wrapper to allow for use of adau1761.sv
in vivado block diagramaxis.sv
AXI stream interfacewavetable.sv
sine-wave generator (uses CORDIC to save memory and keep high resolution audio signal)fm.sv
fm tone generator for use in a synth (uses multiple sine-wave generators)fft.sv
wrapper for 1024-point XFFT IPfundamental_bin_finder.sv
estimates the fundamental frequency of DFT data using harmonic product spectrum (plans to use tonal estimates as well to improve estimate)harmonic_product_spectrum.sv
computes a modified harmonic product spectrum of DFT datapitch_detect.sv
combines fundamental detection with a phase vocoder to estimate the pitch of a windowed frame of time-series datasample_buffer.sv
overlapping FIFO which overlaps input frames (planned to also apply a windowing function)hamming_1024.coe
memory init file for sample_buffer to store window functioni2s_serdes.sv
AXI stream <-> I2S serdesrising_edge.sv
synchronizer and rising edge detector for slow signals (used for bclk
and lrclk
by i2s_serdes
)src/python
pynq python code for initializing codec with AXI_IIC ip
also includes basic skeleton for autotuning and testing out pitch detection algorithms
includes file for experimenting with a fixed-point phase vocoder.
src/test
PRBS checker for i2s controller
Testbenches for other modules (I don’t think any are automated yet; I just wrote these to generate waveforms and see if the design was behaving as I expected)
src/test/vectors
several test vectors for simulation
raw_sawtooth
is raw 24-bit data gathered directly from I2S output of audio codec when playing a sawtooth at the input of the ADCsample_fft
is an FFT of a sawtooth signalsample_timeseries
is a sample sawtooth timeseries signalsawtooth_timeseries
is timeseries data for two sawtoothssrc/model
some C++ code for experimenting with LFSR design
would be useful to add some fixed point and bit-accurate models for the analysis modules, but I don’t have enough time before this project is due.
also includes a C++ model for the input buffer to verify logic for read/write counters
util
process_i2s.py
parses CSV from Saleae logic analyzer analysis of I2S protocol for capturing input signal to FPGA design
See this link for more information on the pitch detection algorithms used(/not used) in this project.