项目描述 ：
This Repository consists of the report and notes from the workshop RTL design with Verilog with SKY130 Technology conducted by VLSI System Design Pvt. Ltd.

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项目地址: git://github.com/ramachandra2002/RTL-design-using-Verilog-with-SKY130-Technology.git

创建时间： 2021-09-01T14:40:07Z
项目社区：https://github.com/ramachandra2002/RTL-design-using-Verilog-with-SKY130-Technology
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